library ieee;
use ieee.std_logic_1164.all;

entity memory is
    port(
    RegWriteInM, MemToRegInM, JumpInM, MemWriteM, BranchM, ZeroM, clk, dump:
        in std_logic;
    WriteRegInM:
        in std_logic_vector(4 downto 0);
    AluResInM, WriteDataM, PCBranchInM:
        in std_logic_vector(31 downto 0);

    RegWriteOutM, MemToRegOutM, JumpOutM,  PCSrcM:
        out std_logic;
    WriteRegOutM:
        out std_logic_vector(4 downto 0);
    AluResOutM, ReadDataM, PCBranchOutM:
        out std_logic_vector(31 downto 0)
    );
end memory;

architecture behav of memory is
    component dmem is
        port(
        a, wd: in std_logic_vector(31 downto 0);
        clk, we, dump: in std_logic;
        rd: out std_logic_vector(31 downto 0)
        );
    end component;

begin
    MEM_dmem: dmem port map(AluResInM, WriteDataM, clk, MemWriteM, dump, 
                            ReadDataM);

    PCSrcM <= ZeroM and BranchM;
    RegWriteOutM <= RegWriteInM;
    MemToRegOutM <= MemToRegInM;
    JumpOutM <= JumpInM;
    AluResOutM <= AluResInM;
    WriteRegOutM <= WriteRegInM;
    PCBranchOutM <= PCBranchInM;
end behav;
